1. Field of the Invention
The present invention relates to a multiplier, and in particular, to a parallel multiplier, in which, for example, used as a multiplier block in a digital signal processor or a video data converter.
2. Background of the Related Art
In general, a multiplier comprises a plurality of basic cells having adders which are arranged in a two-dimensional plane.
FIG. 1 is a block diagram showing a related art array multiplier using the basic cells. Cells C00-C33 have a matrix structure, and are supplied 4-bit multiplicand data a0-a3 and 4-bit multiplier data b0-b3 to produce 8-bit product data. FIG. 2 is the detailed circuit of basic cells in FIG. 1. A basic cell Cij transfers input data ai and bj to the next stage and add the two data to output a carry-out signal and a sum-out signal. ai and bj are applied a 1-bit multiplicand and a 1-bit multiplier, respectively. At this time, each input terminal of the sum-in and the carry-in of the cell C00 is applied the initial value 0. Referring to FIG. 1, the detailed operation of the related art array multiplier will be described as followings.
Cell C00 is applied a0, b0 and 0 as the initial value of a carry-in and a sum-in signal, respectively, and outputs a carry-out signal and a sum-out signal. C01 is applied a0 and the carry-out signal from C00 and C10 is applied a 1, 0 of the carry-in initial value, the sum-out signal from C01 and b0 to conduct an arithmetic operation. The other cells operate as aforementioned. The sum-out signals of cells C00, C10, C20, C30 located at the right end column produce the product data P0-P3. Also, the sum-out signals of cells C30, C31, C32, C33 located at the bottom row produce the product data P4-P7. That is, the related art array multiplier of FIG. 1 comprises a plurality of basic cells arranged in a two-dimensional plane and multiplies 4-bit binary multiplicand data a0-a3 by 4-bit binary multiplier data b0-b3 to produce 8-bit binary product data P0-P7.
The related art array multiplier uses a plurality of basic cells arranged in a two-dimensional plane and conducts ten steps of arithmetic operation. Therefore, there is a problem in the operating speed.
In order to solve the problem, FIGS. 3 and 4 show another related art array multiplier. The pipelined array multiplier of FIG. 3 has a register 10, and obtains a higher speed of operation than the multiplier of FIG. 1 by reducing the operating steps. However, due to the inserted register, the structure is more complex than the array multiplier of FIG. 1, and the required area is increased. Also, the pipelined array multiplier of FIG. 4 has two registers 11 and 12 and a carry propagate adder 40, and it is difficult to obtain a simple and high-integrated circuit. The cells in FIGS. 3 and 4 have the same structure as those in FIG. 1.
The publication "The Design And Analysis Of VLSI Circuits", which is published by Lance A. Glasser and Daniel W. Dobberpuhl, pages 52-55 describes the related art array multipliers of FIGS. 1, 3 and 4 in detail.
As described above, the related art array multipliers comprise a plurality of basic cell arranged in a two-dimensional plane and conduct a multi-step arithmetic operation, thereby having a problem that the operating speed is delayed. Also, registers may be used for a high-speed operation. But it makes the circuit complex and the required area increased.